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<a href="#define-members">Defines</a> &#124;
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle">
<div class="title">System Clock Management</div>  </div>
<div class="ingroups"><a class="el" href="group__clk__group.html">Clock Management</a></div></div>
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<table class="memberdecls">
<tr><td colspan="2"><h2><a name="define-members"></a>
Defines</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gabd8c9eaed83f9b71734a80f4b66742b3">SYSCLK_INIT_MINIMAL_CPUMASK</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga7bd0214b8ad00652adb81da9b5c1b165">SYSCLK_INIT_MINIMAL_HSBMASK</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga25425ac0f90eb3e96a7c303e6707b282">SYSCLK_INIT_MINIMAL_PBAMASK</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga02a23ab95f0213faeb009f4411d0a3aa">SYSCLK_INIT_MINIMAL_PBBMASK</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga5088dc19411a34aad978c46e7ab44525">SYSCLK_INIT_MINIMAL_PBCMASK</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga2ea7011abd3d43ef751313c6fc8c2068">CONFIG_USBCLK_SOURCE</a>&#160;&#160;&#160;USBCLK_SRC_PLL0</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Configuration symbol for the USB generic clock source.  <a href="#ga2ea7011abd3d43ef751313c6fc8c2068"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gac73a11432c1931f5f2daa030eda13923">CONFIG_USBCLK_DIV</a>&#160;&#160;&#160;1</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Configuration symbol for the USB generic clock divider setting.  <a href="#gac73a11432c1931f5f2daa030eda13923"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="func-members"></a>
Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga74da4af4f93582fe3dd33dd75596cdf4">sysclk_priv_enable_module</a> (unsigned int bus_id, unsigned int module_index)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga9d3035baba081035de71adb2dd059ce7">sysclk_priv_disable_module</a> (unsigned int bus_id, unsigned int module_index)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga242399e48a97739c88b4d0c00f6101de">sysclk_init</a> (void)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the synchronous clock system.  <a href="#ga242399e48a97739c88b4d0c00f6101de"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="member-group"></a>
Configuration Symbols</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga7bb6bbe88b7fb398ef8f0befe936e0e7">CONFIG_SYSCLK_SOURCE</a>&#160;&#160;&#160;SYSCLK_SRC_RCSYS</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Initial/static main system clock source.  <a href="#ga7bb6bbe88b7fb398ef8f0befe936e0e7"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaf8bcf7e1ee2ebd2829ebc31be507c6da">CONFIG_SYSCLK_CPU_DIV</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Initial/static CPU/HSB/PBB clock divider (log2)  <a href="#gaf8bcf7e1ee2ebd2829ebc31be507c6da"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaa952d8094a06be420e244e68286c2dbf">CONFIG_SYSCLK_PBA_DIV</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Initial/static PBA clock divider (log2)  <a href="#gaa952d8094a06be420e244e68286c2dbf"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga50962c914daa31fbc279cd4bccf66f98">CONFIG_SYSCLK_PBB_DIV</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Initial/static PBB clock divider (log2)  <a href="#ga50962c914daa31fbc279cd4bccf66f98"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaa31e8248ac7b461b19f7ec827674d16c">CONFIG_SYSCLK_PBC_DIV</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Initial/static PBC clock divider (log2)  <a href="#gaa31e8248ac7b461b19f7ec827674d16c"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="member-group"></a>
System clock source</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga95a749ec308ac07efb9521f2f56ad351">SYSCLK_SRC_RCSYS</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">System RC oscillator.  <a href="#ga95a749ec308ac07efb9521f2f56ad351"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga40595c85aa33898ff3a6cfbd4f8ef7b9">SYSCLK_SRC_OSC0</a>&#160;&#160;&#160;1</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Oscillator 0.  <a href="#ga40595c85aa33898ff3a6cfbd4f8ef7b9"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga9d44be291573208b5b1152f2b6ab1d3a">SYSCLK_SRC_OSC1</a>&#160;&#160;&#160;2</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Oscillator 1.  <a href="#ga9d44be291573208b5b1152f2b6ab1d3a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gacce44c311c87522d71fe51bf4cd37f58">SYSCLK_SRC_PLL0</a>&#160;&#160;&#160;3</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Phase Locked Loop 0.  <a href="#gacce44c311c87522d71fe51bf4cd37f58"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaa46c965047bb81e94066d8df57cb719f">SYSCLK_SRC_PLL1</a>&#160;&#160;&#160;4</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Phase Locked Loop 1.  <a href="#gaa46c965047bb81e94066d8df57cb719f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaa3b782df811d75bf3cf9f4ba8c2266b0">SYSCLK_SRC_RC8M</a>&#160;&#160;&#160;5</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">8 MHz RC oscillator  <a href="#gaa3b782df811d75bf3cf9f4ba8c2266b0"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="member-group"></a>
USB Clock Sources</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga2ba06598e685f870cb3f410f27d75703">USBCLK_SRC_OSC0</a>&#160;&#160;&#160;1</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Use OSC0.  <a href="#ga2ba06598e685f870cb3f410f27d75703"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga5fee2b76449663f9d6c8f7bb34782e77">USBCLK_SRC_OSC1</a>&#160;&#160;&#160;2</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Use OSC1.  <a href="#ga5fee2b76449663f9d6c8f7bb34782e77"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga969e47c6c1f1d38fd2afaf96f6187296">USBCLK_SRC_PLL0</a>&#160;&#160;&#160;3</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Use PLL0.  <a href="#ga969e47c6c1f1d38fd2afaf96f6187296"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gae76666294ec5d1ca2bcfa28061cfae3f">USBCLK_SRC_PLL1</a>&#160;&#160;&#160;4</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Use PLL1.  <a href="#gae76666294ec5d1ca2bcfa28061cfae3f"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="member-group"></a>
Clocks derived from the CPU clock</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga9cbdb318d23dda372bf52dd9b4eb14f5">SYSCLK_OCD</a>&#160;&#160;&#160;AVR32_OCD_CLK_CPU</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">On-Chip Debug system.  <a href="#ga9cbdb318d23dda372bf52dd9b4eb14f5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga619d74a2528721833b011475c6ea1b63">SYSCLK_SYSTIMER</a>&#160;&#160;&#160;AVR32_CORE_CLK_CPU_COUNT</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">COUNT/COMPARE system registers.  <a href="#ga619d74a2528721833b011475c6ea1b63"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="member-group"></a>
Clocks derived from the HSB clock</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga86f02a49fa416cb9618274517c7b6a1b">SYSCLK_SAU_HSB</a>&#160;&#160;&#160;(AVR32_SAU_CLK_HSB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Secure Access Unit HSB interface.  <a href="#ga86f02a49fa416cb9618274517c7b6a1b"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga31a0491a42ddf97870b3218d66921f55">SYSCLK_PDCA_HSB</a>&#160;&#160;&#160;(AVR32_PDCA_CLK_HSB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">PDCA memory interface.  <a href="#ga31a0491a42ddf97870b3218d66921f55"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaeb124548e5e161dfa5f3675721da8a82">SYSCLK_MDMA_HSB</a>&#160;&#160;&#160;(AVR32_MDMA_CLK_HSB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">MDMA memory interface.  <a href="#gaeb124548e5e161dfa5f3675721da8a82"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga8853a36d0721737ccf4f7dfa2287c729">SYSCLK_USBC_DATA</a>&#160;&#160;&#160;(AVR32_USBC_CLK_HSB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">USBC DMA and FIFO interface.  <a href="#ga8853a36d0721737ccf4f7dfa2287c729"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga72bf629f809d2df6ef9877b25712ba76">SYSCLK_CANIF_DATA</a>&#160;&#160;&#160;(AVR32_CANIF_CLK_HSB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">CANIF DMA interface.  <a href="#ga72bf629f809d2df6ef9877b25712ba76"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaa4659bfb4205b768f6846cbfcc2ec7dd">SYSCLK_FLASHC_DATA</a>&#160;&#160;&#160;(AVR32_FLASHC_CLK_HSB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Flash data interface.  <a href="#gaa4659bfb4205b768f6846cbfcc2ec7dd"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga9e400e99e4e4b8f66b3a6d4c7b70611e">SYSCLK_PBA_BRIDGE</a>&#160;&#160;&#160;(AVR32_HMATRIX_CLK_HSB_PBA_BRIDGE % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">HSB&lt;-&gt;PBA bridge.  <a href="#ga9e400e99e4e4b8f66b3a6d4c7b70611e"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaafe37377751bd916833b911fb54de660">SYSCLK_PBB_BRIDGE</a>&#160;&#160;&#160;(AVR32_HMATRIX_CLK_HSB_PBB_BRIDGE % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">HSB&lt;-&gt;PBB bridge.  <a href="#gaafe37377751bd916833b911fb54de660"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga94aa5b488b09dc743ddca6c884660873">SYSCLK_PBC_BRIDGE</a>&#160;&#160;&#160;(AVR32_HMATRIX_CLK_HSB_PBC_BRIDGE % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">HSB&lt;-&gt;PBC bridge.  <a href="#ga94aa5b488b09dc743ddca6c884660873"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaff6d7baf5d4926d22f50ca1bfb738424">SYSCLK_HSB_RAM</a>&#160;&#160;&#160;(AVR32_RAM_CLK_HSB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">HSB RAM.  <a href="#gaff6d7baf5d4926d22f50ca1bfb738424"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga30be147da40e89c8ea7fa6fd0ed30129">SYSCLK_EBI</a>&#160;&#160;&#160;(AVR32_EBI_CLK_HSB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">External Bus Interface.  <a href="#ga30be147da40e89c8ea7fa6fd0ed30129"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga15c11d0c318f04ca3169fda32aea1bee">SYSCLK_PEVC_HSB</a>&#160;&#160;&#160;(AVR32_PEVC_CLK_HSB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral Event Controller.  <a href="#ga15c11d0c318f04ca3169fda32aea1bee"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="member-group"></a>
Clocks derived from the PBA clock</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga14d03e228f6f595a55e1a76040b8f169">SYSCLK_INTC</a>&#160;&#160;&#160;(AVR32_INTC_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Internal interrupt controller.  <a href="#ga14d03e228f6f595a55e1a76040b8f169"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga0f033dbcbfbd2fa9aadc748fb5c18165">SYSCLK_PM</a>&#160;&#160;&#160;(AVR32_PM_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">PM/RTC/EIM configuration.  <a href="#ga0f033dbcbfbd2fa9aadc748fb5c18165"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga49fca3345f07667c997b5ad46db6245b">SYSCLK_SCIF</a>&#160;&#160;&#160;(AVR32_SCIF_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">System Control Interface.  <a href="#ga49fca3345f07667c997b5ad46db6245b"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga6ad9b260e783734ef0e28bb7ac4284a7">SYSCLK_AST</a>&#160;&#160;&#160;(AVR32_AST_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Asynchronous Timer.  <a href="#ga6ad9b260e783734ef0e28bb7ac4284a7"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gae1d87ae47bff0e2e4cab4b417cea4ab1">SYSCLK_WDT</a>&#160;&#160;&#160;(AVR32_WDT_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Timer.  <a href="#gae1d87ae47bff0e2e4cab4b417cea4ab1"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaee7a1048c289fa9dd6abf99eaf64fc46">SYSCLK_EIC</a>&#160;&#160;&#160;(AVR32_EIC_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">External Interrupt Controller.  <a href="#gaee7a1048c289fa9dd6abf99eaf64fc46"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga0bd4c7581ed295f5202efa0631dfe1aa">SYSCLK_FREQM</a>&#160;&#160;&#160;(AVR32_FREQM_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Frequency Meter.  <a href="#ga0bd4c7581ed295f5202efa0631dfe1aa"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaafd65ced01805e6f5dfbd3b08e9aa02c">SYSCLK_GPIO</a>&#160;&#160;&#160;(AVR32_GPIO_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">General-Purpose I/O.  <a href="#gaafd65ced01805e6f5dfbd3b08e9aa02c"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaeeea970aa1d68f0726f6ac7b19882491">SYSCLK_USART0</a>&#160;&#160;&#160;(AVR32_USART0_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">USART 0.  <a href="#gaeeea970aa1d68f0726f6ac7b19882491"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gae2bb545878e7dc4040c1b1e9bab34cdd">SYSCLK_USART2</a>&#160;&#160;&#160;(AVR32_USART2_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">USART 2.  <a href="#gae2bb545878e7dc4040c1b1e9bab34cdd"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga749a1c474f6bcdfb0c71e76d88371572">SYSCLK_USART3</a>&#160;&#160;&#160;(AVR32_USART3_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">USART 3.  <a href="#ga749a1c474f6bcdfb0c71e76d88371572"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga2981d1f5ff381253d3ca94c260bbba01">SYSCLK_SPI1</a>&#160;&#160;&#160;(AVR32_SPI1_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI Controller 1.  <a href="#ga2981d1f5ff381253d3ca94c260bbba01"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga8c2db97d4e5879b8e79271ad4317965c">SYSCLK_TWIM0</a>&#160;&#160;&#160;(AVR32_TWIM0_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">TWI Master 0.  <a href="#ga8c2db97d4e5879b8e79271ad4317965c"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaa6b40c9fda3fc4cf86201bf5d35c60e4">SYSCLK_TWIM1</a>&#160;&#160;&#160;(AVR32_TWIM1_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">TWI Master 1.  <a href="#gaa6b40c9fda3fc4cf86201bf5d35c60e4"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaacb0f0e01d42f813394a6dc51171d0f1">SYSCLK_TWIS0</a>&#160;&#160;&#160;(AVR32_TWIS0_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">TWI Slave 0.  <a href="#gaacb0f0e01d42f813394a6dc51171d0f1"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga8949d9bb62e29e020979d3d428d8fb53">SYSCLK_TWIS1</a>&#160;&#160;&#160;(AVR32_TWIS1_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">TWI Slave 1.  <a href="#ga8949d9bb62e29e020979d3d428d8fb53"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaba7d5c176ee1112b9f590ac775615e36">SYSCLK_PWM</a>&#160;&#160;&#160;(AVR32_PWM_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Pulse Width Modulator.  <a href="#gaba7d5c176ee1112b9f590ac775615e36"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gab8b5a16f6564fc83a5627c61468a635a">SYSCLK_QDEC0</a>&#160;&#160;&#160;(AVR32_QDEC0_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Quadrature Decoder 0.  <a href="#gab8b5a16f6564fc83a5627c61468a635a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga82dd53b7213f5e14889c11d00e9172e8">SYSCLK_QDEC1</a>&#160;&#160;&#160;(AVR32_QDEC1_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Quadrature Decoder 1.  <a href="#ga82dd53b7213f5e14889c11d00e9172e8"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga03be785696a3e76b1b3c6ea6104ac630">SYSCLK_TC1</a>&#160;&#160;&#160;(AVR32_TC1_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Timer/Counter 1.  <a href="#ga03be785696a3e76b1b3c6ea6104ac630"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga399953bbca8665cff37fd74a54196281">SYSCLK_PEVC_REGS</a>&#160;&#160;&#160;(AVR32_PEVC_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral Event Controller.  <a href="#ga399953bbca8665cff37fd74a54196281"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga3d96f4df476b374cae0653bb97b6afa9">SYSCLK_ACIFA0</a>&#160;&#160;&#160;(AVR32_ACIFA0_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Analog Comparator 0.  <a href="#ga3d96f4df476b374cae0653bb97b6afa9"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gae446ad78f0e97d6284514f1f37b77b8e">SYSCLK_ACIFA1</a>&#160;&#160;&#160;(AVR32_ACIFA1_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Analog Comparator 1.  <a href="#gae446ad78f0e97d6284514f1f37b77b8e"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gaca3098d4d705c823acb5a2787a658b2f">SYSCLK_DACIFB0</a>&#160;&#160;&#160;(AVR32_DACIFB0_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">D/A Converter 0.  <a href="#gaca3098d4d705c823acb5a2787a658b2f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gabafc3d95b374fd0543a080132c6a123f">SYSCLK_DACIFB1</a>&#160;&#160;&#160;(AVR32_DACIFB1_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">D/A Converter 1.  <a href="#gabafc3d95b374fd0543a080132c6a123f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga70d3d2ecde2ee79e6cdf0ddf62c5ce14">SYSCLK_AW</a>&#160;&#160;&#160;(AVR32_AW_CLK_PBA % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">aWire UART  <a href="#ga70d3d2ecde2ee79e6cdf0ddf62c5ce14"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="member-group"></a>
Clocks derived from the PBB clock</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga47b081ba5de90a8ea89b8a844e82c14a">SYSCLK_FLASHC_REGS</a>&#160;&#160;&#160;(AVR32_FLASHC_CLK_PBB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Flash Controller registers.  <a href="#ga47b081ba5de90a8ea89b8a844e82c14a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga1f50b29ea7a96a6595b6256118ec6a34">SYSCLK_USBC_REGS</a>&#160;&#160;&#160;(AVR32_USBC_CLK_PBB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">USBB registers.  <a href="#ga1f50b29ea7a96a6595b6256118ec6a34"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga766dce154a1fb38bb35e6e98cd51a9b1">SYSCLK_HMATRIX</a>&#160;&#160;&#160;(AVR32_HMATRIX_CLK_PBB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">HSB Matrix configuration.  <a href="#ga766dce154a1fb38bb35e6e98cd51a9b1"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gafe8483e2e78077a95841ccf52b2da1a5">SYSCLK_SAU_REGS</a>&#160;&#160;&#160;(AVR32_SAU_CLK_PBB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Secure Access Unit register.  <a href="#gafe8483e2e78077a95841ccf52b2da1a5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga8425ce428af87e00693efc695ac3b73e">SYSCLK_SMC_REGS</a>&#160;&#160;&#160;(AVR32_SMC_CLK_PBB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Static Memory Controller registers.  <a href="#ga8425ce428af87e00693efc695ac3b73e"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga386f643ce38c1c6721d07c559a70f365">SYSCLK_SDRAMC_REGS</a>&#160;&#160;&#160;(AVR32_SDRAMC_CLK_PBB % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">SDRAM Controller registers.  <a href="#ga386f643ce38c1c6721d07c559a70f365"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="member-group"></a>
Clocks derived from the PBC clock</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gac83d44e5be54c7b52b86deb4fc338516">SYSCLK_PDCA_PB</a>&#160;&#160;&#160;(AVR32_PDCA_CLK_PBC % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">PDCA peripheral bus interface.  <a href="#gac83d44e5be54c7b52b86deb4fc338516"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gabe01b7586526964dd55bc275e9d40f39">SYSCLK_MDMA_REGS</a>&#160;&#160;&#160;(AVR32_MDMA_CLK_PBC % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">MDMA registers.  <a href="#gabe01b7586526964dd55bc275e9d40f39"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga1acb0cc02d975a6d9d4e92e56a2438a0">SYSCLK_USART1</a>&#160;&#160;&#160;(AVR32_USART1_CLK_PBC % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">USART 1.  <a href="#ga1acb0cc02d975a6d9d4e92e56a2438a0"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga77679d8f496ed32ec8c2476fc28ecf45">SYSCLK_SPI0</a>&#160;&#160;&#160;(AVR32_SPI0_CLK_PBC % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI Controller 0.  <a href="#ga77679d8f496ed32ec8c2476fc28ecf45"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gadf592c60fdfb5213d813f9b5c753f0f7">SYSCLK_CANIF_REGS</a>&#160;&#160;&#160;(AVR32_CANIF_CLK_PBC % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">CANIF registers.  <a href="#gadf592c60fdfb5213d813f9b5c753f0f7"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#gabe7aa477c7c5b3887df1d762a750b04a">SYSCLK_TC0</a>&#160;&#160;&#160;(AVR32_TC0_CLK_PBC % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Timer/Counter 0.  <a href="#gabe7aa477c7c5b3887df1d762a750b04a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga6e40fd22e30fe8f7553443d88ee817aa">SYSCLK_ADCIFA</a>&#160;&#160;&#160;(AVR32_ADCIFA_CLK_PBC % 32)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">A/D Converter.  <a href="#ga6e40fd22e30fe8f7553443d88ee817aa"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="member-group"></a>
System Clock Source and Prescaler configuration</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga9e93d93c137135fee8a1a7102367042e">sysclk_set_prescalers</a> (unsigned int cpu_shift, unsigned int pba_shift, unsigned int pbb_shift, unsigned int pbc_shift)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set system clock prescaler configuration.  <a href="#ga9e93d93c137135fee8a1a7102367042e"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__sysclk__group.html#ga222a121dfaac21b0c0af9d4dcb39496c">sysclk_set_source</a> (uint_fast8_t src)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Change the source of the main system clock.  <a href="#ga222a121dfaac21b0c0af9d4dcb39496c"></a><br/></td></tr>
</table>
<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
<p>The <em>sysclk</em> API covers the <em>system clock</em> and all clocks derived from it. The system clock is a chip-internal clock on which all <em>synchronous clocks</em>, i.e. CPU and bus/peripheral clocks, are based. The system clock is typically generated from one of a variety of sources, which may include crystal and RC oscillators as well as PLLs. The clocks derived from the system clock are sometimes also known as <em>synchronous clocks</em>, since they always run synchronously with respect to each other, as opposed to <em>generic clocks</em> which may run from different oscillators or PLLs.</p>
<p>Most applications should simply call <a class="el" href="group__sysclk__group.html#ga242399e48a97739c88b4d0c00f6101de" title="Initialize the synchronous clock system.">sysclk_init()</a> to initialize everything related to the system clock and its source (oscillator, PLL or DFLL), and leave it at that. More advanced applications, and platform-specific drivers, may require additional services from the clock system, some of which may be platform-specific.</p>
<h2><a class="anchor" id="sysclk_group_platform"></a>
Platform Dependencies</h2>
<p>The sysclk API is partially chip- or platform-specific. While all platforms provide mostly the same functionality, there are some variations around how different bus types and clock tree structures are handled.</p>
<p>The following functions are available on all platforms with the same parameters and functionality. These functions may be called freely by portable applications, drivers and services:</p>
<ul>
<li><a class="el" href="group__sysclk__group.html#ga242399e48a97739c88b4d0c00f6101de" title="Initialize the synchronous clock system.">sysclk_init()</a></li>
<li><a class="el" href="group__sysclk__group.html#ga222a121dfaac21b0c0af9d4dcb39496c" title="Change the source of the main system clock.">sysclk_set_source()</a></li>
<li>sysclk_get_main_hz()</li>
<li>sysclk_get_cpu_hz()</li>
<li>sysclk_get_peripheral_bus_hz()</li>
</ul>
<p>The following functions are available on all platforms, but there may be variations in the function signature (i.e. parameters) and behaviour. These functions are typically called by platform-specific parts of drivers, and applications that aren't intended to be portable:</p>
<ul>
<li>sysclk_enable_peripheral_clock()</li>
<li>sysclk_disable_peripheral_clock()</li>
<li>sysclk_enable_module()</li>
<li>sysclk_disable_module()</li>
<li>sysclk_module_is_enabled()</li>
<li><a class="el" href="group__sysclk__group.html#ga9e93d93c137135fee8a1a7102367042e" title="Set system clock prescaler configuration.">sysclk_set_prescalers()</a></li>
</ul>
<p>All other functions should be considered platform-specific. Enabling/disabling clocks to specific peripherals as well as determining the speed of these clocks should be done by calling functions provided by the driver for that peripheral. </p>
<hr/><h2>Define Documentation</h2>
<a class="anchor" id="gaf8bcf7e1ee2ebd2829ebc31be507c6da"></a><!-- doxytag: member="uc3c/sysclk.h::CONFIG_SYSCLK_CPU_DIV" ref="gaf8bcf7e1ee2ebd2829ebc31be507c6da" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CONFIG_SYSCLK_CPU_DIV&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Initial/static CPU/HSB/PBB clock divider (log2) </p>
<p>Configuration symbol for dividing the CPU clock frequency by <img class="formulaInl" alt="$2^{CONFIG\_SYSCLK\_CPU\_DIV}$" src="form_8.png"/>.</p>
<p>The CPU, HSB and PBA clocks will run at </p>
<p class="formulaDsp">
<img class="formulaDsp" alt="\[ f_{cpu} = \frac{f_{sys}}{2^\mathrm{CONFIG\_SYSCLK\_CPU\_DIV}}\,\mbox{Hz} \]" src="form_4.png"/>
</p>
<p> after initialization.</p>
<p>If this symbol is not defined, the CPU clock frequency is not divided.</p>
<p>This symbol may be defined in <a class="el" href="conf__clock_8h.html">conf_clock.h</a>. </p>

</div>
</div>
<a class="anchor" id="gaa952d8094a06be420e244e68286c2dbf"></a><!-- doxytag: member="uc3c/sysclk.h::CONFIG_SYSCLK_PBA_DIV" ref="gaa952d8094a06be420e244e68286c2dbf" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CONFIG_SYSCLK_PBA_DIV&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Initial/static PBA clock divider (log2) </p>
<p>Configuration symbol for dividing the PBA clock frequency by <img class="formulaInl" alt="$2^{CONFIG\_SYSCLK\_PBA\_DIV}$" src="form_9.png"/>.</p>
<p>The PBA clock will run at </p>
<p class="formulaDsp">
<img class="formulaDsp" alt="\[ f_{PBA} = \frac{f_{sys}}{2^\mathrm{CONFIG\_SYSCLK\_PBA\_DIV}}\,\mbox{Hz} \]" src="form_5.png"/>
</p>
<p> after initialization.</p>
<p>If this symbol is not defined, the PBA clock frequency is not divided.</p>
<p>This symbol may be defined in <a class="el" href="conf__clock_8h.html">conf_clock.h</a>. </p>

</div>
</div>
<a class="anchor" id="ga50962c914daa31fbc279cd4bccf66f98"></a><!-- doxytag: member="uc3c/sysclk.h::CONFIG_SYSCLK_PBB_DIV" ref="ga50962c914daa31fbc279cd4bccf66f98" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CONFIG_SYSCLK_PBB_DIV&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Initial/static PBB clock divider (log2) </p>
<p>Configuration symbol for dividing the PBB clock frequency by <img class="formulaInl" alt="$2^{CONFIG\_SYSCLK\_PBB\_DIV}$" src="form_10.png"/>.</p>
<p>The PBB clock will run at </p>
<p class="formulaDsp">
<img class="formulaDsp" alt="\[ f_{PBB} = \frac{f_{sys}}{2^\mathrm{CONFIG\_SYSCLK\_PBB\_DIV}}\,\mbox{Hz} \]" src="form_6.png"/>
</p>
<p> after initialization.</p>
<p>If this symbol is not defined, the PBB clock frequency is not divided.</p>
<p>This symbol may be defined in <a class="el" href="conf__clock_8h.html">conf_clock.h</a>. </p>

</div>
</div>
<a class="anchor" id="gaa31e8248ac7b461b19f7ec827674d16c"></a><!-- doxytag: member="uc3c/sysclk.h::CONFIG_SYSCLK_PBC_DIV" ref="gaa31e8248ac7b461b19f7ec827674d16c" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CONFIG_SYSCLK_PBC_DIV&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Initial/static PBC clock divider (log2) </p>
<p>Configuration symbol for dividing the PBC clock frequency by <img class="formulaInl" alt="$2^{CONFIG\_SYSCLK\_PBC\_DIV}$" src="form_11.png"/>.</p>
<p>The PBC clock will run at </p>
<p class="formulaDsp">
<img class="formulaDsp" alt="\[ f_{PBC} = \frac{f_{sys}}{2^\mathrm{CONFIG\_SYSCLK\_PBC\_DIV}}\,\mbox{Hz} \]" src="form_7.png"/>
</p>
<p> after initialization.</p>
<p>If this symbol is not defined, the PBC clock frequency is not divided.</p>
<p>This symbol may be defined in <a class="el" href="conf__clock_8h.html">conf_clock.h</a>. </p>

</div>
</div>
<a class="anchor" id="ga7bb6bbe88b7fb398ef8f0befe936e0e7"></a><!-- doxytag: member="uc3c/sysclk.h::CONFIG_SYSCLK_SOURCE" ref="ga7bb6bbe88b7fb398ef8f0befe936e0e7" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CONFIG_SYSCLK_SOURCE&#160;&#160;&#160;SYSCLK_SRC_RCSYS</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Initial/static main system clock source. </p>
<p>The main system clock will be configured to use this clock during initialization. </p>

</div>
</div>
<a class="anchor" id="gac73a11432c1931f5f2daa030eda13923"></a><!-- doxytag: member="conf_clock.h::CONFIG_USBCLK_DIV" ref="gac73a11432c1931f5f2daa030eda13923" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CONFIG_USBCLK_DIV&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Configuration symbol for the USB generic clock divider setting. </p>
<p>Sets the clock division for the USB generic clock. If a USB clock source is selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be defined.</p>
<p>Define this as any value that does not exceed <code>GENCLK_DIV_MAX</code>, and which will give a 48 MHz clock frequency from the selected source. </p>

</div>
</div>
<a class="anchor" id="ga2ea7011abd3d43ef751313c6fc8c2068"></a><!-- doxytag: member="conf_clock.h::CONFIG_USBCLK_SOURCE" ref="ga2ea7011abd3d43ef751313c6fc8c2068" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CONFIG_USBCLK_SOURCE&#160;&#160;&#160;USBCLK_SRC_PLL0</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Configuration symbol for the USB generic clock source. </p>
<p>Sets the clock source to use for the USB. The source must also be properly configured.</p>
<p>Define this to one of the <code>USBCLK_SRC_xxx</code> settings. Leave it undefined if USB is not required. </p>

</div>
</div>
<a class="anchor" id="ga3d96f4df476b374cae0653bb97b6afa9"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_ACIFA0" ref="ga3d96f4df476b374cae0653bb97b6afa9" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_ACIFA0&#160;&#160;&#160;(AVR32_ACIFA0_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Analog Comparator 0. </p>

</div>
</div>
<a class="anchor" id="gae446ad78f0e97d6284514f1f37b77b8e"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_ACIFA1" ref="gae446ad78f0e97d6284514f1f37b77b8e" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_ACIFA1&#160;&#160;&#160;(AVR32_ACIFA1_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Analog Comparator 1. </p>

</div>
</div>
<a class="anchor" id="ga6e40fd22e30fe8f7553443d88ee817aa"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_ADCIFA" ref="ga6e40fd22e30fe8f7553443d88ee817aa" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_ADCIFA&#160;&#160;&#160;(AVR32_ADCIFA_CLK_PBC % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>A/D Converter. </p>

</div>
</div>
<a class="anchor" id="ga6ad9b260e783734ef0e28bb7ac4284a7"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_AST" ref="ga6ad9b260e783734ef0e28bb7ac4284a7" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_AST&#160;&#160;&#160;(AVR32_AST_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Asynchronous Timer. </p>

</div>
</div>
<a class="anchor" id="ga70d3d2ecde2ee79e6cdf0ddf62c5ce14"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_AW" ref="ga70d3d2ecde2ee79e6cdf0ddf62c5ce14" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_AW&#160;&#160;&#160;(AVR32_AW_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>aWire UART </p>

</div>
</div>
<a class="anchor" id="ga72bf629f809d2df6ef9877b25712ba76"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_CANIF_DATA" ref="ga72bf629f809d2df6ef9877b25712ba76" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_CANIF_DATA&#160;&#160;&#160;(AVR32_CANIF_CLK_HSB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>CANIF DMA interface. </p>

</div>
</div>
<a class="anchor" id="gadf592c60fdfb5213d813f9b5c753f0f7"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_CANIF_REGS" ref="gadf592c60fdfb5213d813f9b5c753f0f7" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_CANIF_REGS&#160;&#160;&#160;(AVR32_CANIF_CLK_PBC % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>CANIF registers. </p>

</div>
</div>
<a class="anchor" id="gaca3098d4d705c823acb5a2787a658b2f"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_DACIFB0" ref="gaca3098d4d705c823acb5a2787a658b2f" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_DACIFB0&#160;&#160;&#160;(AVR32_DACIFB0_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>D/A Converter 0. </p>

</div>
</div>
<a class="anchor" id="gabafc3d95b374fd0543a080132c6a123f"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_DACIFB1" ref="gabafc3d95b374fd0543a080132c6a123f" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_DACIFB1&#160;&#160;&#160;(AVR32_DACIFB1_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>D/A Converter 1. </p>

</div>
</div>
<a class="anchor" id="ga30be147da40e89c8ea7fa6fd0ed30129"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_EBI" ref="ga30be147da40e89c8ea7fa6fd0ed30129" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_EBI&#160;&#160;&#160;(AVR32_EBI_CLK_HSB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>External Bus Interface. </p>

</div>
</div>
<a class="anchor" id="gaee7a1048c289fa9dd6abf99eaf64fc46"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_EIC" ref="gaee7a1048c289fa9dd6abf99eaf64fc46" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_EIC&#160;&#160;&#160;(AVR32_EIC_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>External Interrupt Controller. </p>

</div>
</div>
<a class="anchor" id="gaa4659bfb4205b768f6846cbfcc2ec7dd"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_FLASHC_DATA" ref="gaa4659bfb4205b768f6846cbfcc2ec7dd" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_FLASHC_DATA&#160;&#160;&#160;(AVR32_FLASHC_CLK_HSB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Flash data interface. </p>

</div>
</div>
<a class="anchor" id="ga47b081ba5de90a8ea89b8a844e82c14a"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_FLASHC_REGS" ref="ga47b081ba5de90a8ea89b8a844e82c14a" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_FLASHC_REGS&#160;&#160;&#160;(AVR32_FLASHC_CLK_PBB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Flash Controller registers. </p>

</div>
</div>
<a class="anchor" id="ga0bd4c7581ed295f5202efa0631dfe1aa"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_FREQM" ref="ga0bd4c7581ed295f5202efa0631dfe1aa" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_FREQM&#160;&#160;&#160;(AVR32_FREQM_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Frequency Meter. </p>

</div>
</div>
<a class="anchor" id="gaafd65ced01805e6f5dfbd3b08e9aa02c"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_GPIO" ref="gaafd65ced01805e6f5dfbd3b08e9aa02c" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_GPIO&#160;&#160;&#160;(AVR32_GPIO_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>General-Purpose I/O. </p>

</div>
</div>
<a class="anchor" id="ga766dce154a1fb38bb35e6e98cd51a9b1"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_HMATRIX" ref="ga766dce154a1fb38bb35e6e98cd51a9b1" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_HMATRIX&#160;&#160;&#160;(AVR32_HMATRIX_CLK_PBB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>HSB Matrix configuration. </p>

</div>
</div>
<a class="anchor" id="gaff6d7baf5d4926d22f50ca1bfb738424"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_HSB_RAM" ref="gaff6d7baf5d4926d22f50ca1bfb738424" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_HSB_RAM&#160;&#160;&#160;(AVR32_RAM_CLK_HSB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>HSB RAM. </p>

</div>
</div>
<a class="anchor" id="gabd8c9eaed83f9b71734a80f4b66742b3"></a><!-- doxytag: member="sysclk.c::SYSCLK_INIT_MINIMAL_CPUMASK" ref="gabd8c9eaed83f9b71734a80f4b66742b3" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_INIT_MINIMAL_CPUMASK</td>
        </tr>
      </table>
</div>
<div class="memdoc">
<b>Value:</b><div class="fragment"><pre class="fragment">((1 &lt;&lt; <a class="code" href="group__sysclk__group.html#ga9cbdb318d23dda372bf52dd9b4eb14f5" title="On-Chip Debug system.">SYSCLK_OCD</a>)                                                 \
                | (1 &lt;&lt; <a class="code" href="group__sysclk__group.html#ga619d74a2528721833b011475c6ea1b63" title="COUNT/COMPARE system registers.">SYSCLK_SYSTIMER</a>))
</pre></div>
</div>
</div>
<a class="anchor" id="ga7bd0214b8ad00652adb81da9b5c1b165"></a><!-- doxytag: member="sysclk.c::SYSCLK_INIT_MINIMAL_HSBMASK" ref="ga7bd0214b8ad00652adb81da9b5c1b165" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_INIT_MINIMAL_HSBMASK</td>
        </tr>
      </table>
</div>
<div class="memdoc">
<b>Value:</b><div class="fragment"><pre class="fragment">((1 &lt;&lt; <a class="code" href="group__sysclk__group.html#gaa4659bfb4205b768f6846cbfcc2ec7dd" title="Flash data interface.">SYSCLK_FLASHC_DATA</a>)                                         \
                | (1 &lt;&lt; <a class="code" href="group__sysclk__group.html#ga9e400e99e4e4b8f66b3a6d4c7b70611e" title="HSB&lt;-&gt;PBA bridge.">SYSCLK_PBA_BRIDGE</a>)                                     \
                | (1 &lt;&lt; <a class="code" href="group__sysclk__group.html#gaff6d7baf5d4926d22f50ca1bfb738424" title="HSB RAM.">SYSCLK_HSB_RAM</a>))
</pre></div>
</div>
</div>
<a class="anchor" id="ga25425ac0f90eb3e96a7c303e6707b282"></a><!-- doxytag: member="sysclk.c::SYSCLK_INIT_MINIMAL_PBAMASK" ref="ga25425ac0f90eb3e96a7c303e6707b282" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_INIT_MINIMAL_PBAMASK</td>
        </tr>
      </table>
</div>
<div class="memdoc">
<b>Value:</b><div class="fragment"><pre class="fragment">((1 &lt;&lt; <a class="code" href="group__sysclk__group.html#ga14d03e228f6f595a55e1a76040b8f169" title="Internal interrupt controller.">SYSCLK_INTC</a>)                                                \
                | (1 &lt;&lt; <a class="code" href="group__sysclk__group.html#gaafd65ced01805e6f5dfbd3b08e9aa02c" title="General-Purpose I/O.">SYSCLK_GPIO</a>)                                           \
                | (1 &lt;&lt; <a class="code" href="group__sysclk__group.html#ga49fca3345f07667c997b5ad46db6245b" title="System Control Interface.">SYSCLK_SCIF</a>)                                           \
                | (1 &lt;&lt; <a class="code" href="group__sysclk__group.html#ga0f033dbcbfbd2fa9aadc748fb5c18165" title="PM/RTC/EIM configuration.">SYSCLK_PM</a>))
</pre></div>
</div>
</div>
<a class="anchor" id="ga02a23ab95f0213faeb009f4411d0a3aa"></a><!-- doxytag: member="sysclk.c::SYSCLK_INIT_MINIMAL_PBBMASK" ref="ga02a23ab95f0213faeb009f4411d0a3aa" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_INIT_MINIMAL_PBBMASK&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div>
<div class="memdoc">

</div>
</div>
<a class="anchor" id="ga5088dc19411a34aad978c46e7ab44525"></a><!-- doxytag: member="sysclk.c::SYSCLK_INIT_MINIMAL_PBCMASK" ref="ga5088dc19411a34aad978c46e7ab44525" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_INIT_MINIMAL_PBCMASK&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div>
<div class="memdoc">

</div>
</div>
<a class="anchor" id="ga14d03e228f6f595a55e1a76040b8f169"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_INTC" ref="ga14d03e228f6f595a55e1a76040b8f169" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_INTC&#160;&#160;&#160;(AVR32_INTC_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Internal interrupt controller. </p>

</div>
</div>
<a class="anchor" id="gaeb124548e5e161dfa5f3675721da8a82"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_MDMA_HSB" ref="gaeb124548e5e161dfa5f3675721da8a82" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_MDMA_HSB&#160;&#160;&#160;(AVR32_MDMA_CLK_HSB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>MDMA memory interface. </p>

</div>
</div>
<a class="anchor" id="gabe01b7586526964dd55bc275e9d40f39"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_MDMA_REGS" ref="gabe01b7586526964dd55bc275e9d40f39" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_MDMA_REGS&#160;&#160;&#160;(AVR32_MDMA_CLK_PBC % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>MDMA registers. </p>

</div>
</div>
<a class="anchor" id="ga9cbdb318d23dda372bf52dd9b4eb14f5"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_OCD" ref="ga9cbdb318d23dda372bf52dd9b4eb14f5" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_OCD&#160;&#160;&#160;AVR32_OCD_CLK_CPU</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>On-Chip Debug system. </p>

</div>
</div>
<a class="anchor" id="ga9e400e99e4e4b8f66b3a6d4c7b70611e"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_PBA_BRIDGE" ref="ga9e400e99e4e4b8f66b3a6d4c7b70611e" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_PBA_BRIDGE&#160;&#160;&#160;(AVR32_HMATRIX_CLK_HSB_PBA_BRIDGE % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>HSB&lt;-&gt;PBA bridge. </p>

</div>
</div>
<a class="anchor" id="gaafe37377751bd916833b911fb54de660"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_PBB_BRIDGE" ref="gaafe37377751bd916833b911fb54de660" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_PBB_BRIDGE&#160;&#160;&#160;(AVR32_HMATRIX_CLK_HSB_PBB_BRIDGE % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>HSB&lt;-&gt;PBB bridge. </p>

</div>
</div>
<a class="anchor" id="ga94aa5b488b09dc743ddca6c884660873"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_PBC_BRIDGE" ref="ga94aa5b488b09dc743ddca6c884660873" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_PBC_BRIDGE&#160;&#160;&#160;(AVR32_HMATRIX_CLK_HSB_PBC_BRIDGE % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>HSB&lt;-&gt;PBC bridge. </p>

</div>
</div>
<a class="anchor" id="ga31a0491a42ddf97870b3218d66921f55"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_PDCA_HSB" ref="ga31a0491a42ddf97870b3218d66921f55" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_PDCA_HSB&#160;&#160;&#160;(AVR32_PDCA_CLK_HSB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>PDCA memory interface. </p>

</div>
</div>
<a class="anchor" id="gac83d44e5be54c7b52b86deb4fc338516"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_PDCA_PB" ref="gac83d44e5be54c7b52b86deb4fc338516" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_PDCA_PB&#160;&#160;&#160;(AVR32_PDCA_CLK_PBC % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>PDCA peripheral bus interface. </p>

</div>
</div>
<a class="anchor" id="ga15c11d0c318f04ca3169fda32aea1bee"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_PEVC_HSB" ref="ga15c11d0c318f04ca3169fda32aea1bee" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_PEVC_HSB&#160;&#160;&#160;(AVR32_PEVC_CLK_HSB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Peripheral Event Controller. </p>

</div>
</div>
<a class="anchor" id="ga399953bbca8665cff37fd74a54196281"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_PEVC_REGS" ref="ga399953bbca8665cff37fd74a54196281" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_PEVC_REGS&#160;&#160;&#160;(AVR32_PEVC_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Peripheral Event Controller. </p>

</div>
</div>
<a class="anchor" id="ga0f033dbcbfbd2fa9aadc748fb5c18165"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_PM" ref="ga0f033dbcbfbd2fa9aadc748fb5c18165" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_PM&#160;&#160;&#160;(AVR32_PM_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>PM/RTC/EIM configuration. </p>

</div>
</div>
<a class="anchor" id="gaba7d5c176ee1112b9f590ac775615e36"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_PWM" ref="gaba7d5c176ee1112b9f590ac775615e36" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_PWM&#160;&#160;&#160;(AVR32_PWM_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Pulse Width Modulator. </p>

</div>
</div>
<a class="anchor" id="gab8b5a16f6564fc83a5627c61468a635a"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_QDEC0" ref="gab8b5a16f6564fc83a5627c61468a635a" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_QDEC0&#160;&#160;&#160;(AVR32_QDEC0_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Quadrature Decoder 0. </p>

</div>
</div>
<a class="anchor" id="ga82dd53b7213f5e14889c11d00e9172e8"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_QDEC1" ref="ga82dd53b7213f5e14889c11d00e9172e8" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_QDEC1&#160;&#160;&#160;(AVR32_QDEC1_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Quadrature Decoder 1. </p>

</div>
</div>
<a class="anchor" id="ga86f02a49fa416cb9618274517c7b6a1b"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SAU_HSB" ref="ga86f02a49fa416cb9618274517c7b6a1b" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SAU_HSB&#160;&#160;&#160;(AVR32_SAU_CLK_HSB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Secure Access Unit HSB interface. </p>

</div>
</div>
<a class="anchor" id="gafe8483e2e78077a95841ccf52b2da1a5"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SAU_REGS" ref="gafe8483e2e78077a95841ccf52b2da1a5" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SAU_REGS&#160;&#160;&#160;(AVR32_SAU_CLK_PBB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Secure Access Unit register. </p>

</div>
</div>
<a class="anchor" id="ga49fca3345f07667c997b5ad46db6245b"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SCIF" ref="ga49fca3345f07667c997b5ad46db6245b" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SCIF&#160;&#160;&#160;(AVR32_SCIF_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>System Control Interface. </p>

</div>
</div>
<a class="anchor" id="ga386f643ce38c1c6721d07c559a70f365"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SDRAMC_REGS" ref="ga386f643ce38c1c6721d07c559a70f365" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SDRAMC_REGS&#160;&#160;&#160;(AVR32_SDRAMC_CLK_PBB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>SDRAM Controller registers. </p>

</div>
</div>
<a class="anchor" id="ga8425ce428af87e00693efc695ac3b73e"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SMC_REGS" ref="ga8425ce428af87e00693efc695ac3b73e" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SMC_REGS&#160;&#160;&#160;(AVR32_SMC_CLK_PBB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Static Memory Controller registers. </p>

</div>
</div>
<a class="anchor" id="ga77679d8f496ed32ec8c2476fc28ecf45"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SPI0" ref="ga77679d8f496ed32ec8c2476fc28ecf45" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SPI0&#160;&#160;&#160;(AVR32_SPI0_CLK_PBC % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>SPI Controller 0. </p>

</div>
</div>
<a class="anchor" id="ga2981d1f5ff381253d3ca94c260bbba01"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SPI1" ref="ga2981d1f5ff381253d3ca94c260bbba01" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SPI1&#160;&#160;&#160;(AVR32_SPI1_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>SPI Controller 1. </p>

</div>
</div>
<a class="anchor" id="ga40595c85aa33898ff3a6cfbd4f8ef7b9"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SRC_OSC0" ref="ga40595c85aa33898ff3a6cfbd4f8ef7b9" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SRC_OSC0&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Oscillator 0. </p>

</div>
</div>
<a class="anchor" id="ga9d44be291573208b5b1152f2b6ab1d3a"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SRC_OSC1" ref="ga9d44be291573208b5b1152f2b6ab1d3a" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SRC_OSC1&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Oscillator 1. </p>

</div>
</div>
<a class="anchor" id="gacce44c311c87522d71fe51bf4cd37f58"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SRC_PLL0" ref="gacce44c311c87522d71fe51bf4cd37f58" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SRC_PLL0&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Phase Locked Loop 0. </p>

</div>
</div>
<a class="anchor" id="gaa46c965047bb81e94066d8df57cb719f"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SRC_PLL1" ref="gaa46c965047bb81e94066d8df57cb719f" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SRC_PLL1&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Phase Locked Loop 1. </p>

</div>
</div>
<a class="anchor" id="gaa3b782df811d75bf3cf9f4ba8c2266b0"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SRC_RC8M" ref="gaa3b782df811d75bf3cf9f4ba8c2266b0" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SRC_RC8M&#160;&#160;&#160;5</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>8 MHz RC oscillator </p>

</div>
</div>
<a class="anchor" id="ga95a749ec308ac07efb9521f2f56ad351"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SRC_RCSYS" ref="ga95a749ec308ac07efb9521f2f56ad351" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SRC_RCSYS&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>System RC oscillator. </p>

</div>
</div>
<a class="anchor" id="ga619d74a2528721833b011475c6ea1b63"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_SYSTIMER" ref="ga619d74a2528721833b011475c6ea1b63" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_SYSTIMER&#160;&#160;&#160;AVR32_CORE_CLK_CPU_COUNT</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>COUNT/COMPARE system registers. </p>

</div>
</div>
<a class="anchor" id="gabe7aa477c7c5b3887df1d762a750b04a"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_TC0" ref="gabe7aa477c7c5b3887df1d762a750b04a" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_TC0&#160;&#160;&#160;(AVR32_TC0_CLK_PBC % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Timer/Counter 0. </p>

</div>
</div>
<a class="anchor" id="ga03be785696a3e76b1b3c6ea6104ac630"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_TC1" ref="ga03be785696a3e76b1b3c6ea6104ac630" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_TC1&#160;&#160;&#160;(AVR32_TC1_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Timer/Counter 1. </p>

</div>
</div>
<a class="anchor" id="ga8c2db97d4e5879b8e79271ad4317965c"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_TWIM0" ref="ga8c2db97d4e5879b8e79271ad4317965c" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_TWIM0&#160;&#160;&#160;(AVR32_TWIM0_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>TWI Master 0. </p>

</div>
</div>
<a class="anchor" id="gaa6b40c9fda3fc4cf86201bf5d35c60e4"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_TWIM1" ref="gaa6b40c9fda3fc4cf86201bf5d35c60e4" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_TWIM1&#160;&#160;&#160;(AVR32_TWIM1_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>TWI Master 1. </p>

</div>
</div>
<a class="anchor" id="gaacb0f0e01d42f813394a6dc51171d0f1"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_TWIS0" ref="gaacb0f0e01d42f813394a6dc51171d0f1" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_TWIS0&#160;&#160;&#160;(AVR32_TWIS0_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>TWI Slave 0. </p>

</div>
</div>
<a class="anchor" id="ga8949d9bb62e29e020979d3d428d8fb53"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_TWIS1" ref="ga8949d9bb62e29e020979d3d428d8fb53" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_TWIS1&#160;&#160;&#160;(AVR32_TWIS1_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>TWI Slave 1. </p>

</div>
</div>
<a class="anchor" id="gaeeea970aa1d68f0726f6ac7b19882491"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_USART0" ref="gaeeea970aa1d68f0726f6ac7b19882491" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_USART0&#160;&#160;&#160;(AVR32_USART0_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>USART 0. </p>

</div>
</div>
<a class="anchor" id="ga1acb0cc02d975a6d9d4e92e56a2438a0"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_USART1" ref="ga1acb0cc02d975a6d9d4e92e56a2438a0" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_USART1&#160;&#160;&#160;(AVR32_USART1_CLK_PBC % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>USART 1. </p>

</div>
</div>
<a class="anchor" id="gae2bb545878e7dc4040c1b1e9bab34cdd"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_USART2" ref="gae2bb545878e7dc4040c1b1e9bab34cdd" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_USART2&#160;&#160;&#160;(AVR32_USART2_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>USART 2. </p>

</div>
</div>
<a class="anchor" id="ga749a1c474f6bcdfb0c71e76d88371572"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_USART3" ref="ga749a1c474f6bcdfb0c71e76d88371572" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_USART3&#160;&#160;&#160;(AVR32_USART3_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>USART 3. </p>

</div>
</div>
<a class="anchor" id="ga8853a36d0721737ccf4f7dfa2287c729"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_USBC_DATA" ref="ga8853a36d0721737ccf4f7dfa2287c729" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_USBC_DATA&#160;&#160;&#160;(AVR32_USBC_CLK_HSB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>USBC DMA and FIFO interface. </p>

</div>
</div>
<a class="anchor" id="ga1f50b29ea7a96a6595b6256118ec6a34"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_USBC_REGS" ref="ga1f50b29ea7a96a6595b6256118ec6a34" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_USBC_REGS&#160;&#160;&#160;(AVR32_USBC_CLK_PBB % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>USBB registers. </p>

</div>
</div>
<a class="anchor" id="gae1d87ae47bff0e2e4cab4b417cea4ab1"></a><!-- doxytag: member="uc3c/sysclk.h::SYSCLK_WDT" ref="gae1d87ae47bff0e2e4cab4b417cea4ab1" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SYSCLK_WDT&#160;&#160;&#160;(AVR32_WDT_CLK_PBA % 32)</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Watchdog Timer. </p>

</div>
</div>
<a class="anchor" id="ga2ba06598e685f870cb3f410f27d75703"></a><!-- doxytag: member="uc3c/sysclk.h::USBCLK_SRC_OSC0" ref="ga2ba06598e685f870cb3f410f27d75703" args="" -->
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define USBCLK_SRC_OSC0&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Use OSC0. </p>

</div>
</div>
<a class="anchor" id="ga5fee2b76449663f9d6c8f7bb34782e77"></a><!-- doxytag: member="uc3c/sysclk.h::USBCLK_SRC_OSC1" ref="ga5fee2b76449663f9d6c8f7bb34782e77" args="" -->
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          <td class="memname">#define USBCLK_SRC_OSC1&#160;&#160;&#160;2</td>
        </tr>
      </table>
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<p>Use OSC1. </p>

</div>
</div>
<a class="anchor" id="ga969e47c6c1f1d38fd2afaf96f6187296"></a><!-- doxytag: member="uc3c/sysclk.h::USBCLK_SRC_PLL0" ref="ga969e47c6c1f1d38fd2afaf96f6187296" args="" -->
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          <td class="memname">#define USBCLK_SRC_PLL0&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Use PLL0. </p>

</div>
</div>
<a class="anchor" id="gae76666294ec5d1ca2bcfa28061cfae3f"></a><!-- doxytag: member="uc3c/sysclk.h::USBCLK_SRC_PLL1" ref="gae76666294ec5d1ca2bcfa28061cfae3f" args="" -->
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          <td class="memname">#define USBCLK_SRC_PLL1&#160;&#160;&#160;4</td>
        </tr>
      </table>
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<p>Use PLL1. </p>

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</div>
<hr/><h2>Function Documentation</h2>
<a class="anchor" id="ga242399e48a97739c88b4d0c00f6101de"></a><!-- doxytag: member="uc3c/sysclk.h::sysclk_init" ref="ga242399e48a97739c88b4d0c00f6101de" args="(void)" -->
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          <td class="memname">void sysclk_init </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Initialize the synchronous clock system. </p>
<p>This function will initialize the system clock and its source. This includes:</p>
<ul>
<li>Mask all synchronous clocks except for any clocks which are essential for normal operation (for example internal memory clocks).</li>
<li>Set up the system clock prescalers as specified by the application's configuration file.</li>
<li>Enable the clock source specified by the application's configuration file (oscillator or PLL) and wait for it to become stable.</li>
<li>Set the main system clock source to the clock specified by the application's configuration file.</li>
</ul>
<p>Since all non-essential peripheral clocks are initially disabled, it is the responsibility of the peripheral driver to re-enable any clocks that are needed for normal operation. </p>

</div>
</div>
<a class="anchor" id="ga9d3035baba081035de71adb2dd059ce7"></a><!-- doxytag: member="sysclk.c::sysclk_priv_disable_module" ref="ga9d3035baba081035de71adb2dd059ce7" args="(unsigned int bus_id, unsigned int module_index)" -->
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          <td class="memname">void sysclk_priv_disable_module </td>
          <td>(</td>
          <td class="paramtype">unsigned int&#160;</td>
          <td class="paramname"><em>bus_id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">unsigned int&#160;</td>
          <td class="paramname"><em>module_index</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div>
<div class="memdoc">

</div>
</div>
<a class="anchor" id="ga74da4af4f93582fe3dd33dd75596cdf4"></a><!-- doxytag: member="sysclk.c::sysclk_priv_enable_module" ref="ga74da4af4f93582fe3dd33dd75596cdf4" args="(unsigned int bus_id, unsigned int module_index)" -->
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      <table class="memname">
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          <td class="memname">void sysclk_priv_enable_module </td>
          <td>(</td>
          <td class="paramtype">unsigned int&#160;</td>
          <td class="paramname"><em>bus_id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">unsigned int&#160;</td>
          <td class="paramname"><em>module_index</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div>
<div class="memdoc">

</div>
</div>
<a class="anchor" id="ga9e93d93c137135fee8a1a7102367042e"></a><!-- doxytag: member="uc3c/sysclk.h::sysclk_set_prescalers" ref="ga9e93d93c137135fee8a1a7102367042e" args="(unsigned int cpu_shift, unsigned int pba_shift, unsigned int pbb_shift, unsigned int pbc_shift)" -->
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          <td class="memname">void sysclk_set_prescalers </td>
          <td>(</td>
          <td class="paramtype">unsigned int&#160;</td>
          <td class="paramname"><em>cpu_shift</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">unsigned int&#160;</td>
          <td class="paramname"><em>pba_shift</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">unsigned int&#160;</td>
          <td class="paramname"><em>pbb_shift</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">unsigned int&#160;</td>
          <td class="paramname"><em>pbc_shift</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Set system clock prescaler configuration. </p>
<p>This function will change the system clock prescaler configuration to match the parameters.</p>
<dl class="note"><dt><b>Note:</b></dt><dd>The parameters to this function are device-specific.</dd></dl>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramname">cpu_shift</td><td>The CPU clock will be divided by <img class="formulaInl" alt="$2^{cpu\_shift}$" src="form_0.png"/> </td></tr>
    <tr><td class="paramname">pba_shift</td><td>The PBA clock will be divided by <img class="formulaInl" alt="$2^{pba\_shift}$" src="form_1.png"/> </td></tr>
    <tr><td class="paramname">pbb_shift</td><td>The PBB clock will be divided by <img class="formulaInl" alt="$2^{pbb\_shift}$" src="form_2.png"/> </td></tr>
    <tr><td class="paramname">pbc_shift</td><td>The PBC clock will be divided by <img class="formulaInl" alt="$2^{pbc\_shift}$" src="form_3.png"/> </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a class="anchor" id="ga222a121dfaac21b0c0af9d4dcb39496c"></a><!-- doxytag: member="uc3c/sysclk.h::sysclk_set_source" ref="ga222a121dfaac21b0c0af9d4dcb39496c" args="(uint_fast8_t src)" -->
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          <td class="memname">void sysclk_set_source </td>
          <td>(</td>
          <td class="paramtype">uint_fast8_t&#160;</td>
          <td class="paramname"><em>src</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Change the source of the main system clock. </p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramname">src</td><td>The new system clock source. Must be one of the constants from the <em>System Clock Sources</em> section. </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
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